1. Field of the Invention
The present invention relates to chip carriers. More particularly, the present invention relates to quad flat no-lead (QFN) chip carriers and chip package structures.
2. Background and Related Art
Semiconductor packages are known to take a variety of forms. Similarly, chip carriers used in semiconductor packages take a variety of forms. One type of chip package currently used employs a leadframe arrangement. According to the type of leads used in the leadframe, a quad flat package (QFP) can be divided into quad flat packages with I-type leads (QFI), quad flat packages with J-types leads (QFJ) and quad flat packages no-lead (QFN). Because the outer end of the leads of the leadframe are uniformly cut along the four edges of a chip package, this latter type of package is also referred to as a quad flat no-lead chip carrier.
FIG. 1 shows a plan view of the bottom side of a conventional QFN chip carrier. This is the side of the QFN opposite to the side to which the chip is mounted. Leadframe 1 comprises die paddle 5 and leads 6. As shown, leads 6 are arranged around the periphery of the four-sided leadframe. The arrangement shown has 8 leads per side for a total of 32 leads. Typically, leadframe 1 comprises a flat piece of copper that has a pattern (the leads and the die paddle) which pattern may, for example, be etched or stamped out of the flat piece of copper.
As shown in the cross-sectional view of FIG. 2, die or chip 7 is mounted on die paddle 5. As employed herein, the terms die and chip are used interchangeably to mean a semiconductor chip. Lead contacts 3 typically comprise plating layer 9, such as silver plating, and plating layer 11, such as solder, both plated onto copper lead 6. Gold wires 13, for example, may form connections between chip 7 and lead contacts 3. Gold wire 15 may, for example, form a ground connection. The arrangement is then encased in a mold compound 17.
Normally, for second level interconnect, the QFN chip carrier is mounted on a printed circuit board (PCB). The mounting process involves soldering the lead contacts 3 and die paddle 5 to pads on the PCB. However, because the copper of lead contacts 3 and die paddle 5 protrudes from mold compound 17 by a small amount (e.g. 0.05 mm), soldering the lead contacts to pads on the PCB can be problematic. FIG. 3 shows solder connections 19 between copper leads 6 of leadframe 3 and pads 21, and solder connection 20 between die paddle 5 and conductive pad 22 on PCB 23.
Several problems arise as a result of the limited protrusion of stand-off of copper lead contacts 3 and die paddle 5 of leadframe 1. For example, the limited protrusion limits the ability of the solder to wet due to the small area on the side of copper leads 6. In addition, the amount of solder used must be limited in order to reduce solder shorting between leads and, accordingly, helps improve yield. Yields are also affected due to the tendency of the QFN to float on the solder paste at assembly, which floating acts to cause the QFN to misalign with the PCB pads during solder reflow. Yields are further affected due to opens caused by lead co-planarity and by the QFN being tilted when placed in the solder paste.